Chip Placement with RL

  • Control and optimization
  • Semiconductor


Due to the high complexity of integrated circuit (IC) logic design, chip floor-planning and placement and routing (PnR) can take from few weeks to months. Most design companies face a significant challenge in optimizing semiconductor chip design and production automation for the purpose of improving performance while reducing costs.


Based on geometrical data of logic elements, our approach employs reinforcement learning (RL) with virtual chip simulator to optimize chip's floor-plan and PnR. In other words, to train RL model aimed to optimizing element placement, we develop chip simulation environments and placement algorithms.


When compared to manual work done by human experts , power consumption, performance, and density are all improved, and time spent in chip placement procedure is greatly reduced. Our method can potentially relieve human experts' workload and make manufacturing environments more efficient.

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